Results 1 to 5 of 5

Thread: - MIPS

Hybrid View

Previous Post Previous Post   Next Post Next Post
  1. #1
    Get a Mac moridinbg's Avatar
    Join Date: Dec:2004
    Location: 0x00000000
    Posts: 4,211

    - MIPS

    QUESTION 3
    We have a RISC processor with register-register arithmetic instructions that have the format
    R1 <- R2opR3. The pipeline for these instructions runs with a 100 MHz clock with the following
    stages: instruction fetch = 2 clocks, instruction decode = 1 clock, fetch operands = 1 clock,
    execute = 2 clocks, and store result = 1 clock.
    1. At what rate (in MIPS) can we execute register-register instructions that have no data
    dependencies with other instructions?
    , 7 , ~14MIPS
    2 -> 50MIPS o.O





    2 ...
    , ?!

  2. #2
    Registered User
    Join Date: Aug:2003
    Location:
    Posts: 175
    , 2 . , 9 ( , ). :
    • N ?

  3. #3
    ɐ-əpoɔᴉu⋂ ɐ ə anrieff's Avatar
    Join Date: Apr:2004
    Location: Sofia
    Posts: 8,448
    100 / 2 = 50 MIPS, (): 100 pipeline-, 2 - , . execute 3 , 33.33.. MIPS, 3 -
    , . .
    "640K ught to be enough for anybody" - Bill Gates, 1981
    ::Machine specs::Fract::AGG::::Baileys::blog::YouTube channel

  4. #4
    Get a Mac moridinbg's Avatar
    Join Date: Dec:2004
    Location: 0x00000000
    Posts: 4,211
    , , . , 25MIPS , .

  5. #5
    philosophus duratea icaci's Avatar
    Join Date: Oct:2006
    Location: Aachen
    Posts: 2,698
    , 7 , . ,
    Internet - it doesn't make you stupid, it just makes your stupidity more accessible to others

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •  

Copyright © 1999-2011 . .
iskamPC.com | mobility.BG | Bloody's Techblog | | 3D Vision Blog |