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7th February 2011 23:45 #1
- MIPS
, 7 , ~14MIPSQUESTION 3
We have a RISC processor with register-register arithmetic instructions that have the format
R1 <- R2opR3. The pipeline for these instructions runs with a 100 MHz clock with the following
stages: instruction fetch = 2 clocks, instruction decode = 1 clock, fetch operands = 1 clock,
execute = 2 clocks, and store result = 1 clock.
1. At what rate (in MIPS) can we execute register-register instructions that have no data
dependencies with other instructions?
2 -> 50MIPS o.O

2 ...
, ?!
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8th February 2011 00:09 #2Registered User
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8th February 2011 10:33 #3
100 / 2 = 50 MIPS, (): 100 pipeline-, 2 - , . execute 3 , 33.33.. MIPS, 3 -
, . .
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8th February 2011 12:45 #4
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8th February 2011 14:42 #5
, 7 , . ,
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