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  1. #1
    ãîëÅì ðÚï acdc's Avatar
    Join Date: Jul:2001
    Location: Ñîôèÿ
    Posts: 15,473

    Ìàðêåòîëîã=ÈÇÌÀÌÍÈÊ!!!!

    Íåçíàåõ êúäå äà ïóñíà òàçè òåìà, íî ìèñëÿ, ÷å òóê å íàé-óäà÷íî.
    Åòî òóê èìà åäèí ìíîãî êðàñíîðå÷èâ ïðèìåð, êàê ìàðêåòîëîçèòå çàðèáÿâàò è îìàãüîñâàò íåïðîñâåòåíèÿ ïîòðåáèòåëè, êîåòî å ìíîãî àêòóàëíî, çàùîòî íàâñÿêúäå ñìå ñå íàãëåäàëè íàñëóøàëè íà ãðúìêè îáåùàíèÿ è ðåêëàìè åäâà ëè íå, ÷å ñå êà÷âàìå íà êîñìè÷åñêà ñîâàëêà.

    http://www.xbitlabs.com/articles/edi...t2006-3_5.html

    È ïî òè÷íî åòî òîâà "Albatron says that mainboards with digital clock-generator...."
    Íàïðàâî ñúì èçóìåí îò çëèÿ ãåíèé, íà òîçè ìàðêåòîëîã äåòî å èçìèñëèë òîâà, è êàê ùå ñå âúðæå âñåêè êëîêúð áåç ïîçíàíèÿ ïî åëåêòðîíèêà

    P.S Íåçíàåõ, ÷å äîñåãà ñà ñëàãàëè àíàëîãîâè êëîê-ãåíåðàòîðè â äúíàòà ñè, êàêòî è êîíêóðåíöèÿòà èì. Òî ìîæå áè çàòîâà, íå ñà ñå êëîêâàëè äîñòàòú÷íî

  2. #2
       
    Join Date: Aug:2003
    Location:  
    Posts: 8,103
    Tyan èìàò dual Opteron äúíî ñ "digital VRM" - òîâà ñúùîòî ëè òðÿáâà äà çíà÷è, ùîòî áÿõà îêàñòðèëè åëåêòðîëèòíèòå êîíäåíçàòîðè îêîëî öîêëèòå !?
    ASRock X99 Extreme6/3.1 | Core i7 6950X | 32GB G.Skill DDR4-3200 | Samsung 970 PRO 1TB | MSI GeForce RTX 4080 Gaming X Trio

  3. #3
    Íàøèÿò ÷åðåí êîòàðàê Private's Avatar
    Join Date: Jan:2002
    Location: Ñîôèÿ
    Posts: 32,164
    Ñíèìêà îò òóê:



    Öèòàò îò òóê:

    Until now, clock signals have been supplied by an analog circuit—the phase-locked loop (PLL)
    —which dates back to the 1930s. At the price points required by mainstream electronic products,
    PLL architecture forces serious compromises onto system developers:

    * Achieving high frequency resolution to maximize system performance
    produces noisy clock signals that reduce system performance

    * Frequency changes that dynamically optimize performance and power
    consumption are difficult to control, leading to system failures

    * Large chips are required to integrate independent synthesizers that
    individually optimize each subsystem's operation

    Öèòàò îò òóê:

    The startup says TotalClock can regulate the clock speed of PC processors and
    other components, such as buses that shuttle data and memory, on the fly.

    Its goal is to replace phase-locked loop chips with the TotalClock chip,
    which it says can better regulate the speed of PC hardware and thus
    boost desktops' performance and or extend battery life in notebooks.

    Although they're given little thought by anyone but PC makers or enthusiasts,
    PLLs (phase-locked loops) have a huge effect on the performance of PCs, one analyst said.
    Last edited by Private; 14th March 2006 at 15:32. Reason: äîáàâåíî èíôî, ïðàâîïèñ
    -= All our life, we are beta testers =-
    -= Âíèìàíèå! Âúçìîæíî å ïîñòîâåòå ìè äà ñúäúðæàò õóìîð, [ñàìî]èðîíèÿ è ñàðêàçúì! =-
    -= Êàêâè òåìè ìå ðàäâàò è çàùî =-= Îòèäîõà ñè äîáðè õîðà: Fo , goblin =-

  4. #4
    Registered User
    Join Date: Jul:2001
    Location: Ñîôèÿ
    Posts: 15,344
    âèå ñå ñìååòå àìà îíèÿ ÷è÷êî îò Õ-áèò ëàáñ ùå íàëàïà êèíòèòå çà ðåêëàìà

    öåëèÿ îòáîð êëîêåðè ùå êëîêâà òî÷íî àëáàòðîíà è ùå ãî èçêàðà ÍÎÌÅÐ 1

    äîêòîð Òîì ðÿïà äà ÿäå ïðåä Õ-áèò ëàáñ

    Àìè èçìèøëéîòèíàòà ÊÓÀÄ SLI ?
    CoreDuo@MacosX

  5. #5
    Registered User
    Join Date: Jun:2004
    Location: Ñîôèÿ
    Posts: 113
    Õè õè õè, âå÷å ãè å ëàïíàë êèíòèòå

  6. #6
    EVGA RTX 3090 FTW3 V I P E R's Avatar
    Join Date: Dec:2001
    Location: Áëàãîåâãðàä
    Posts: 7,043
    Àç êàòî ãî ãëåäàì êîëêî å "õúðáàâî" òîâà äúíî äîðè è òàêàâà ðåêëàìà íÿìà äà ìó ïîìîãíå.

    À òîâà íå å åäèíñòâåíîòî äúíî ñ 975 ïðèòåæàâàùî digital clock-generator

    Äîñåãà ïîäïèðàõà À64-êèòå ñ êàêâè ëè íå ðåêëàìè, ñåãà å ðåä íà Êîíðîó è íîâèòå äúíöà, êîèòî ãî ïîääúðæàò.
    If you can read this, then you aren't "well" Îverclockåd yet...!!!

  7. #7
    ãîëÅì ðÚï acdc's Avatar
    Join Date: Jul:2001
    Location: Ñîôèÿ
    Posts: 15,473
    Àààà, ïîìàãà, ïîìàãà. Íå ñè êðèâè äóøàòà, â èíòåðåñ íà èñòèíàòà ñè èìà âñè÷êî (ïðåäîñòàòú÷íî SATA êîíåêòîðè è 7 phase VRM, êîåòî å íàïúëíî èçëèøíî çàùîòî è åäíî 4phase ùå ñâúðøè ñúùàòà ðàáîòà, àìà òîâà å äðóã âúïðîñ) íî òîâà íå îçíà÷àâà íèùî, è õîðàòà çàðèáÿâàò ïîòðåáèòåëèòå ñ äðóãî Áàñ òè ëîâÿ, ÷å ùå èìà äîñòà çàðèáåíè õîðà, à ïúê íÿêîè êîèòî íå çíàÿò êàêâî å òîâà è àêî ñà ïî-ëþáîïèòíè è âëåçíàò íà ñàéòà íà timelab, íàïðàâî ùå èì ñå ðåçíàò "êàí÷åòàòà" êàòî ïðî÷åòàò êîëêî "äîïîòîïíà" è "íåñúâúðøåíà" å áèëà òàçè òåõíîëîãèÿ (PLL) îò 30-å ãîäèíè íà ìèíàëèÿ âåê êîÿòî å ïîëçâàíà. Íàïðàâî þçúðà ùå ñå ÷óäè, è ùå öúêà ñ åçèê êàê èçîáùî áèâøåòî ìó äúíî å óñïÿëî è ñ 1MHz äà ñå êëîêíå íàä äèôîëò ÷åñòîòàòà.
    felix, íå ãî çíàì òîçè digital VRM, ñåãà ùå ãî ïîãëåäíà íà ñàéòà íà Tyan

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